1. Field of the Invention
This invention relates in general to integrated circuits (ICs) fabricated on semiconductor wafers, and, more specifically, to devices and methods for isolating a short-circuited IC from other ICs on a semiconductor wafer so that, for example, probe testing may proceed on the other ICs on the wafer despite the presence of the short-circuited IC.
2. State of the Art
As shown in FIG. 1, integrated circuits (ICs) 10 are small electronic circuits formed on the surface of a wafer 12 of semiconductor material, such as silicon, in an IC manufacturing process referred to as "fabrication." Once fabricated, ICs 10 are electronically probed to evaluate a variety of their electronic characteristics. Probing typically involves positioning needle-like probes (not shown) onto bond pads 14 on the surfaces of ICs 10 to test the ICs 10 using various electronic signals supplied through the probes. As described in U.S. Pat. Nos. 5,059,899 and 5,214,657 to Farnworth et al., in some cases, ICs 10 are tested using test probes that contact probe pads 16 positioned on the surface of a semiconductor wafer 12 rather than, or in addition to, contacting bond pads 14 on the ICs 10.
Sometimes shorts develop in some of the ICs 10 on a semiconductor wafer 12 as a result of fabrication errors. These shorts can interfere with the probe testing described above in a variety of ways. For example, in some instances, a supply voltage V.sub.cc, provided to ICs 10 on a wafer 12 through probes contacting bond pads 14 on the ICs 10 or probe pads 16 on the wafer 12, may be shorted to ground through one of the ICs 10. As a result, over-current protection circuitry, such as a fuse, present in testing equipment that provides the supply voltage V.sub.cc to the probes, will likely "trip" the equipment off-line, causing a brief but significant delay in the manufacturing of ICs 10 while the equipment is reset. In addition, such a V.sub.cc -to-ground short in an IC 10 may make the entire wafer 12 untestable until the IC 10 with the short is identified and either repaired or disconnected, which involves a separate manual process that can cause additional delays in the manufacturing process.
In other instances, a test signal V.sub.TEST supplied to a group of ICs 10 on a semiconductor wafer 12 through a probe pad 16 on the wafer 12 may be distorted for all of the ICs 10 in the group by, for example, a V.sub.TEST -to-ground or a V.sub.TEST -to- V.sub.cc short in one of the ICs 10 in the group. This distortion may interfere with probe testing of all of the ICs 10 in the group, and may require that the IC 10 with the short be manually identified and repaired or disconnected before the ICs 10 in the group can be successfully probe tested.
Therefore, there is a need in the art for a device and method for isolating a short-circuited IC on a semiconductor wafer from other ICs on the wafer. Preferably, such a device and method should isolate a short-circuited IC before the IC interferes with probe testing of other ICs so the probe testing can continue uninterrupted.